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Integrated Circuit Systems, Inc.
ICS1522
User-ProgrammableVideo Clock Generator/ Line-Locked Clock Regenerator
General Description
The ICS1522 is a very high performance monolithic phaselocked loop (PLL) frequency synthesizer. Utilizing ICS's advanced CMOS mixed-mode technology, the ICS1522 provides a low-cost solution for high-end video clock generation where synchronization to an external video source is required. The ICS1522 has differential video clock outputs (CLK+ and CLK-) that are compatible with industry standard video DAC. Operating frequencies are fully programmable with direct control provided for reference divider, feedback divider and postscaler.
Features
* Serial programming: Feedback and reference divisors, VCO gain, phase comparator gain, relative phase and test modes. Supports high-resolution graphics - Differential CLK out-puts to 230 MHz Eliminates need for multiple ECL output voltage controlled crystal oscillators and external components Fully-programmable synthesizer capability - not just a clock multiplier Line-locked clock generation capability; 15 - 100 kHz External feedback loop capability allows graphics system to be used as the feedback divisor with synchronous switchover to internal feedback Small footprint 24-pin SOIC Coarse and fine phase adjustment permits precise clocking in video recovery application
* * * * *
* *
Applications Block Diagram
* * * LCD Projector Systems Multimedia video line locking Genlock applications
1522RevF050697P
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS1522
Overview
The ICS1522 is ideally suited to provide the graphics system clock signals required by high-performance video DACs. Fully programmable feedback and reference divider capability allow virtually any frequency to be generated, not just simple multiples of the reference frequency. The ICS1522 uses the latest generation of frequency synthesis techniques developed by ICS and is completely suitable for the most demanding video applications.
Output Post-scaler
A programmable post-scaler may be inserted between the VCO and the CLK+ and CLK- outputs of the ICS1522. This is useful in generating of lower frequencies, as the VCO has been optimized for high-frequency operation. The post-scaler allows the selection of dividing the VCO frequency by either 1, 2, 4 or 8.
PLL Synthesizer Ratiometric Mode
Description
-
Load Clock Divider
The ICS1522 has an additional programmable divider (referred to in the Block Diagram as the load counter) that is used to generate the LOAD clock frequency for the video DAC. The modulus of this divider may be set to 3, 4, 5, 6, 8, or 10 under register control. The design of this divider permits the output duty factor to be 50/50, even when odd modulus is selected. The input frequency to this divider is the output of the output post-scaler described above.
The ICS1522 generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is a closed-loop feedback system that drives the output frequency to be ratiometrically related to the reference frequency pro-vided to the PLL (see Block Diagram). The reference frequency is generated by an on-chip crystal oscillator or the reference frequency may be applied to the ICS1522 from an external frequency source, typically horizontal sync from another dis-play system. The phase-frequency detector shown in the Block Diagram drives the voltage-controlled oscillator, or VCO, to a frequency that will cause the two inputs to the phasefrequency detector to be matched in frequency and phase. This occurs when: F(VCO): = F(XTAL1) . Feedback Divider Reference Divider This expression is exact; that is, the accuracy of the output frequency depends solely on the reference frequency provided to the part (assuming correctly programmed dividers). The VCO gain is programmable, which permits the ICS1522 to be optimized for best performance at all operating frequencies. The feedback divider may be programmed for any modulus from 64 to 2048 in steps of one followed by a divide by 1, 2, 4 or 8 feedback post-scaler. The reference divider may be programmed for any modulus from 1 to 1024 in steps of one.
Digital Inputs - ICS1522
The programming of the ICS1522 is performed serially by using the SDATA, SCLK, and SELn pins to load the 7, 11 bit internal memory locations. Single bit changes are accomplished by addressing the appro-priate memory location and writing only 11 bits of data, not by writing all 77 data bits. For proper programming of the ICS1522, it is important that all transitions of the SELn input occur during the same state of the SCLK input. SDATA is shifted into a 15 bit serial register on the rising edge of SCLK while SELn is low. The first bit loaded is R/ Wn followed by a 3 bit address and 11 bit data (both address & data are LSB first). When a rising edge of SCLK occurs while SELn is high (SDATA ignored), the contents of the serial register are loaded into the addressed 11 bit memory location if R/Wn is low. If R/Wn is high upon the above condition, the data from the addressed memory location is loaded into the serial shift register and SDATA is set as an output. The 3 bit address and 11 bit data will be serially shifted out of the ICS1522 on the SDATA pin on the rising edge of SCLK while SELn is low (see Timing Diagram). An additional control pin on the ICS1522, PDEN can be used to disable the phase-frequency detector in line-locked applica-tions. When disabled, the phase detector will ignore any inputs and allow the VCO to coast. This feature is useful in systems using composite sync.
2
ICS1522
Output Description
The differential output drivers, CLK+ and CLK-, are current-mode and are designed to drive resistive terminations in a complementary fashion. The outputs are currentsinking only, with the amount of sink current programmable via the IPRG pin. The sink current, which is steered to either CLK+ or CLK-, is four times the current supplied to the IPRG pin. For most applications, a resistor from VDDO to IPRG will set the current to the necessary precision.
Reference Oscillator and Crystal Selection
The ICS1522 has circuitry on-board to implement a Pierce oscillator with the addition of a quartz crystal and two external loading capacitors (EXTREF bit must be set to logic 0). Pierce oscillators operate the crystal in anti- (also called parallel-) resonant mode. Series-resonant crystals may also be used with the ICS1522. Be aware that the oscillation frequency will be slightly higher than the frequency that is stamped on the can (typically 0.025-0.05%). As the entire operation of the phase-locked loop depends on having a stable reference frequency, we recommend that the crystal be mounted as closely as possible to the package. Avoid routing digital signals or the ICS1522 outputs underneath or near these traces. It is also desirable to ground the crystal can to the ground plane, if possible. If an external reference frequency source is to be used with the ICS1522, it is important that it be jitter-free. The rising and falling edges of that signal should be fast and free of noise for best results. The loop phase is locked to the rising edge of the XTAL1/EXTREF input signal, if REF_POL is set to logic 0. Additionally, the EXTREF bit should be set to logic 1 to switch in a TTL-compatible buffer at this input.
Line-Locked Operation
Some video applications require a clock to be generated that is a multiple of horizontal sync. The ICS1522 supports this mode of operation. The reference divider should be set to divide by one and the desired polarity (rising or falling) of lock edge should be selected. By using the phase detector hardware disable mode (PDEN), the PLL can be made to free-run at the beginning of the vertical interval of the external video, and can be reactivated at its completion.
External Feedback Operation
The ICS1522 option also supports the inclusion of an external counter as the feedback divider of the PLL. This mode is useful in graphic systems that must be "genlocked" to external video sources. When the FBK_SEL bit is set to logic 0, the phasefrequency detector will use the EXTFBK pin as its feedback input. The loop phase will be locked to the rising edges of the signal applied to the EXTFBK input if FBK_POL is set to logic 0 Synchronous switchover to the internal feedback can be ac-complished by setting the FBK-SEL bit to logic 1 while an active feedback source exists on the EXTFBK pin.
24-Pin SOIC
Fine Phase Adjustment
The ICS1522 has the capability of adjusting the pixel clock phase relative to the input reference phase. Entire pixels can be added or removed under register control with sub-pixel adjust-ment accomplished by a control voltage on the FINE input pin. By utilizing the fine phase adjust, after first synchronously switching from external feedback to internal feedback, the graphics system phase can be precisely controlled relative to the input horizontal sync. 3
ICS1522
Power-On Initialization
The ICS1522 has an internal power-on reset circuit that sets the frequency of the CLK+and CLK- outputs to be half the crystal or reference frequency assuming that they are between 10 MHz and 25 MHz (refer to default settings in Register Definition). Because the power-on reset circuit is on the VDD supply, and because that supply is filtered, care must be taken to allow the reset to de-assert before programming. A safe guideline is to allow 20 microseconds after the VDD supply reaches four volts.
Power Supplies and Decoupling
The ICS1522 has three VSS pins to reduce the effects of package inductance. Both pins are connected to the same potential on the die (the ground bus). These pins should connect to the ground plane of the video board as close to the package as is possible. The ICS1522 has a VDDO pin which is the supply of +5 volt power to all output drivers. This pin should be connected to the power plane (or bus) using standard high-frequency decoupling practice. That is, capacitors should have low series inductance and be mounted close to the ICS1522. The VDD pin is the power supply pin for the PLL synthesizer circuitry and other lower current digital functions. We recommend that RC decoupling or zener regulation be provided for this pin (as shown in the recommended application circuitry). This will allow the PLL to "track" through power supply fluctuations without visible effects.
Board Test Support
It is often desirable to statically control the levels of the output pins for circuit board test. The ICS1522 supports this through a register programmable mode, AUXEN. When this mode is set, AUXCLK will directly control the logic levels of the CLK+ and CLK- pins while OMUX1, OMUX2, OMUX3, and OMUX4 will control OUT1, OUT2, OUT3 and OUT4, respectively.
Pin Discriptions
PIN NUMBER PIN NAME TYPE DESCRIPTION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
IPUMP SDATA SCLK SELn AVDD XTAL1/EXTREF XTAL2 FINE VSS VSS OUT4 OUT3 VDDO OUT2 OUT1 VSS IPRG CLKCLK+ VDD PDEN EXTFBK EXTVCO VVCO
OUT IN/OUT IN IN PWR IN OUT IN PWR PWR OUT OUT PWR OUT OUT PWR IN OUT OUT PWR IN IN IN IN
Charge Pump output (External loop filter applications) Serial Data Input/Output Serial Clock Input Serial Port enable (active Low) Analog +5 Volt Supply External Reference Input / Xtal Oscillator Input Xtal Oscillator Output Fine Phase Adjust Input Ground Ground Output 4 Output 3 Output Driver +5 Volt Supply Output 2 Output 1 Ground Output Driver Current Programming Input Differential CLK - Output Differential CLK + Output Digital +5 Volt Supply Phase Detector Enable (Active High) External Feedback Input External VCO input VCO Control Voltage Input (External loop filter applications)
4
ICS1522
ICS1522 Register Definition
REG# 0 BIT(S) 0-10 BIT REF. F[0:10] DESCRIPTION Feedback Divider (Default=04F, Modulus=80) Divides the VCO by the set modulus Modulus Range=64 to 2048; Modulus=Value+1 Feedback Sync Pulse LO (Default=03) Feedback Divider output, but with programmable phase; LO[0:7] VCO(2) VCO(1) VCO(0) VCO GAIN
1 2 3
0-7 0-7 0-9
LO[0:7] HI[0:7] R[0:9]
3 4
10 0-2
REF_POL VCO[0:2]
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
10 MHz/V 15 MHz/V 20 MHz/V 25 MHz/V 45 MHz/V 60 MHz/V 75 MHz/V 90 MHz/V
5
ICS1522
REG# 4
BIT(S) 3-5
BIT REF. PFD (0;2)
DESCRIPTION Phase Frequency Detector Gain
PFD(2) PFD(1) PFD(0) PFD GAIN FINE PHASE ADJ.
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
.2344uA/2rad .9375uA/2rad 3.750uA/2rad 15.00uA/2rad 1.875uA/2rad 7.500uA/2rad 30.00uA/2rad 120.0uA/2rad
3ns/V 3ns/V 3ns/V 3ns/V 6ns/V 6ns/V 1.5ns/V .375ns/V
4
6
PDEN
Phase Frequency Detector Enable (Default=1) 0=PFD Disable; 1=PFD Enable Loop Filter Select (Default=1) 0=External Loop Filter (IPUMP & VVCO active) 1=Internal Loop Filter VCO Select (Default=1) 0=External VCO (EXTVCO active) 1=Internal VCO Feedback Divider Clock Input Select (Default=0) 0=VCO; 1=OUT1 Must be set to one. Feedback Select (Default=1) 0=External Feedback (EXTFBK active) 1=Internal Feedback An active external feedback signal at EXTFBK is necessary to synchronously switch to internal. External Feedback Polarity (Default=0) 0=Positive Edge; 1=Negative Edge Addition of 1 VCO Cycle (Default=0) Toggle (0 to 1 to 0) to add 1 VCO cycle. Removal of 1 VCO Cycle (Default=0) Toggle (0 to 1 to 0) to remove 1 VCO cycle.
4
7
INT_FLT
4
8
INT_VCO
4
9
CLK_SEL
4 5
10 0
RESERVED FBK_SEL
5
1
FBK_POL
5
2
ADD
5
3
SWLW
6
ICS1522
REG# 5
BIT(S) 4-5
BIT REF. PDA(0:1)
DESCRIPTION Output Post-scaler (Default=0) Input=VCO; Output = Differential Output
PFD(2) PFD(0) DIVIDE BY
0 0 1 1
0 1 0 1
8 4 2 1
5
6-7
PDB(0:1)
Feedback Post-scaler (Default=3) Input=Feedback Divider; Output=PFD
PDB(1) PDB(0) DIVIDE BY
0 0 1 1
0 1 0 1
8 4 2 1
5
8
LD_LG
Fine Phase Adjust Lead/Lag (Default=1) 1=FBK will lag REF at input to PFD 0=FBK will lead REF at input to PFD Fine Phase Adjust Enable (Default=)) 0=Disable; 1=Enable Must be set to one. Load Counter (Default=7)
L(2) L(1) L(0) DIVIDE BY
5
9
F_EN
5 6
10 0-2
RESERVED L(0:2)
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
31-pos, 0-neg 4 pos edge 4 neg edge 51-neg, 0-pos 6 pos edge 8 neg edge 8 neg edge 10 neg edge
7
ICS1522
REG# 6
BIT(S) 3
BIT REF. OMUX1
DESCRIPTION OUT1 Select (Default=0) 0=Load Counter Output 1=Diff. Output Divided by 4 at 0 Degrees OUT1 will track OMUX1 when AUXEN=1 OUT2 Select (Default=0) 0=Internal Feedback Pulse 1=Diff. Output Divided by 4 at 90 Degrees OUT2 will track OMUX2 when AUXEN=1\ OUT3 Select (Default=0) 0=Feedback Sync Pulse LO 1=Diff. Output Divided by 4 at 180 Degrees OUT3 will track OMUX3 when AUXEN=1 OUT4 Select (Default=1) 0=Feedback Sync Pulse HI 1=Diff. Output Divided by 4 at 270 Degrees OUT4 will track OMUX4 when AUXEN=1 Output Reset (Default=0) When set to one, the CLK+ output is kept high and the CLK-output is kept low. When returned to zero, the CLK+ and CLK-outputs will resume toggling on a rising edge of the OUT1 output (programmed for Load Counter) within +/- 1 clock period. Output Test Mode (Default=0) 0=Normal Output Operation 1=Output Test Mode (see OMUX1-4 and AUXCLK) Output Clock when in Test Mode (Default=0) CLK+ and CLK- will track AUXCLK when AUXEN=1 XTAL/EXTREF Input Buffer (Default=0) 0=Crystal Input Operation 1=External Reference Input Operation
6
4
OMUX2
6
5
OMUX3
6
6
OMUX4
6
7
DACRST
6
8
AUXEN
6 6
9 10
AUXCLK EXTREF
8
ICS1522
Serial ProgrammingTiming Diagram
NOTES: 1. R/Wn, READ=1 and WRITE=0 2. Address and data transmitted least significant bit first 3. 16 Positive-edge clocks required for complete data read/write (1-R/Wn, 3-Address, 11-Data, and 1 load data W/SELn HIGH) 4. SELn's positive and negative transitions must occur on the same state of SCLK 5. An ICS1522 read consists of two consecutive cycles (1st cycle - SDATA is an input, 2nd cycle - SDATA is an output)
9
ICS1522
Absolute Maximum Ratings
VDD, VDDO (measured to VSS) ................. 7.0V Digital Inputs VSS ....................................... -0.5 to VDD to 0.5V Digital Outputs VSS ..................................... -0.5 to VDDO to +0.5V Storage temperature .................................... -65 to 150 C DC Characteristics Junction temperature ................................... 175 C Soldering temperature ................................. 260C
Recommended Operating Conditions
VDD, VDDO (measured to VSS) ................ 4.75 to 5.25V Operating Temperature (Ambient) ............ 0 to 70C
DC Characteristics
TTL-Compatible Inputs PDEN, EXTFBK, SDATA, SCLK, SELn, and XTAL1/EXTREF (when EXTREF bit set to 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Input Input Input Input
High Voltage Low Voltage Hysteresis High Current
Vih Vil Iih Iil Cin Vih=VDD Vil=0.0
2.0 VSS - 0.5 .20 -
VDD+0.5 0.8 .60 10 200 8
V V V A A pF
Input Low Current Input Capacitance
EXTVCO Input
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Input High Voltage Input Low Voltage
CLK+, CLK - Outputs
Vx h Vx 1
3.75 VS- 0.5
VD+5 1.25
V V
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Differential Output Voltage
OUT1, OUT2, OUT3, OUT4 Outputs
0.6
-
V
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Output High Voltage (I OH=4.0mA) Output Low Voltage (I ol=8.0mA)
2.4 -
0.4
V V
10
ICS1522
AC Characteristics
SYMBOL PARAMETER MIN TYP MAX UNITS
Fvco Fxtal Cpar FHSYNC Txhi Txlo TJIT Tlock Idd Iddo
VCO Frequency Crystal Frequency Crystal Oscillator Loading Capacitance Horizontal Sync Rate XTAL1 High Time (when driven externally) XTAL1 Low Time (when driven externally) Phase Jitter (see Note 1) PLL Acquire Time (to within 1%) VDD Supply Current VDDO Supply Current (excluding CLK+/- termination)
ANALOG INPUTS
14 5 20 15 8 8
230 20 100
MHz MHz pF kHz ns ns ns ms mA mA
1 500 15 20
TFINE VFINE A A A A A A A A A TSKEW FCLK VCO PFD
Fine Phase Adjustment Range Control Voltage for FINE FINE Input Bias Current Capacitance of FINE Input Bandwidth of FINE Input (3dB)
DIGITAL INPUT
0 0
15 VDD/2 20 100
ns VDC nA pf kHz ns ns ns MHz ns ns ps MHz MHz/V mA/2prad
0.5 10 10 20
1.5
SELn, SDATA Setup Time SELn, SDATA Hold Time SCLK Pulse Width (Thi or Tlo) SCLK Frequency Phase-frequency detector enable time Phase-frequency detector disable time
20 50 50 500 230
GAINS
DIGITAL OUTPUTS
Time Skew between CLK+, CLKCLK+ and CLK- Clock Rate VCO Gain, VCO(0:2) Phase Detector Gain, PFD (0:2) 10 .23
90 120
Note 1: TJIT is the total uncertainty of the phase measured at the start of a video line on a 350 MHz oscilloscope under these conditions: HSYNC pin driven with crystal oscillator at 48.363 kHz; FVCO = 65.000 MHz; M =0 (divide by 1 on the output; and N = 1343 (1344 clocks per line).
11
ICS1522
Memory Definition
ICS1522 memory is loaded serially with the least significant bit clocked into the device first. After the R/Wn bit, the next three bits of the programming word (15 bits) hold the memory location to be loaded. The least significant 11 bits are the data to be loaded (see Timing Diagram).
MEMORY DATA BITS ADDRESS 000 001 001 010 010 011 011 100 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 110 110 110 110 110 110 110 110 110 0-10 0-7 8-10 0-7 8-10 0-9 10 0-2 3-5 6 7 8 9 10 0 1 2 3 4-5 6-7 8 9 10 0-2 3 4 5 6 7 8 9 10
DEFAULT VALUES (HEX) 04F 03 0 06 0 013 0 4 3 1 1 1 0 1 1 0 0 0 0 3 1 0 1 7 0 0 0 1 0 0 0 0
NAME F(0:10) LO(0:7) A HI(0:7) A R(0:9) REF VCO(0:2) PFD(0:2) PDEN INT_FLT INT_VCO CLK_SEL Reserved FBK_SEL FBK_POL ADD SWLW PDA(0:1) PDB(0:1) LD_LG F_EN Reserved L(0:2) OMUX1 OMUX2 OMUX3 OMUX4 DACRST AUXEN AUXCLK EXTREF
DESCRIPTION Feedback Divider Modulus (Modulus = Value +1) M Counter Lo Sync State Don't Care M Counter Hi Sync State Don't Care Reference Divider Modulus (Modulus = Value + 1) POL External Reference Polarity (1 =Invert) VCO Gain Phase Detector Gain Phase Detector Enable (1 =Enable) Internal Loop Filter (1 = Internal) Internal VCO (1 = Internal) Internal feedback input clock select (0 = VCO Output) Reserved - Set to One Feedback Select (1 =Internal) External Feedback Polarity (1 =Invert) Addition of 1 VCO Cycle (0 to 1 = Add) Removal of 1 VCO Cycle (0 to 1 = Swallow) Output Post-Scaler Feedback Post-Scaler Fine Phase Adj. Lead/Lag (1=Lead) Fine Phase Adj. Enable (1=Enable) Reserved - Set to One Load Counter OUT1 Select (0 = Load Cntr, 1 = Div By 4 0Deg) OUT2 Select (0 = Int Fbk, 1 = Div By 4 90Deg) OUT3 Select (0 = Sync Lo, 1 = Div By 4 180Deg) OUT4 Select (0 = Sync Hi, 1 = Div By 4 270Deg) Output Reset (CLK+ = 1, CLK- = 0) Output Test Mode (1 = Test, See Board Test Support) Output Clock When in Test Mode XTAL/EXTREF Input Buffer (1=EXTREF)
12
ICS1522
Pixel-by-Pixel Adjustment of Genlocking Phase (ICS1522 Application)
To understand the operation of the pixel-by-pixel phase adjust-ment feature, imagine that the modulus of the onchip divider is equivalent to the graphics system overall divide. Also, imagine that the overflow of the internal divider occurs at the same time as the overflow of the graphics system line counter. Initial synchronization is accomplished by switching from the external feedback source (graphics system HSYNC) to the internal feedback. Let us assume that we are now using the internal divider. Now, imagine that the programmed value of the divider (really a prescaler) is increased by one for a single passthrough that prescaler (think of this as "swallowing" a feedback pulse). We will lose exactly one CLK period of phase in the feedback path. The VCO will speed up momentarily to compensate for that, and re-lock the loop. In doing so, the graphics system will receive exactly one extra CLK cycle, advancing the phase of the graphics system HSYNC by one CLK period relative to the reference HSYNC. In a similar fashion, we can decrease the programmed value of the prescaler ("adding" a pulse) to retard the phase of the graphics system. Additionally, subpixel phase adjustment is provided through varying the voltage at the FINE input pin.
24-Pin SOIC Package Ordering Information
ICS1522M
Example:
ICS XXXX M
Package Type
M=SOIC
Device Type (consists of 3 or 4 digit numbers) Prefix
ICS=Standard Device
13
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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